Principal Physical Design Engineer

- Own the full RTL2GDS flow on advanced process nodes - synthesis, floorplan, placement, CTS, routing, and signoff - across Astera's connectivity product portfolio

- Drive block- and chip-level place & route strategy, congestion resolution, and routing convergence on high-frequency, high-density designs

- Architect clock tree synthesis and clocking topology to meet skew, latency, and power targets

- Lead tapeout execution: final ECO closure, GDS handoff, and post-tapeout support through fab

- Drive multi-mode multi-corner STA closure, low-power implementation (UPF/CPF), and IR/EM analysis to signoff

- Own physical verification (LVS, DRC, antenna, ERC) and reliability signoff through clean closure

- Define methodology for ECO flows, hierarchical timing, and full-chip signoff sign-around

- Partner with RTL, DFT, analog/mixed-signal, package, and CAD teams to converge on floorplan, clocking, and power delivery strategies

- Establish and evolve physical design methodology, scripts, and flows across the team

- Mentor engineers, drive design reviews, and represent Physical Design in program-level technical decisions

- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

- 8+ years of physical design experience with multiple tapeouts on advanced process nodes (7nm or below)

- Deep expertise in synthesis, place & route, CTS, and timing closure using industry-standard tools (Synopsys Fusion Compiler / ICC2, Cadence Innovus, PrimeTime)

- Strong command of low-power design techniques (multi-Vt, power gating, DVFS, UPF)

- Proven track record delivering high-frequency, high-complexity SoC blocks or full-chip implementations to production

- Experience with high-speed SerDes-heavy designs, PCIe Gen 6/7, or UALink/UCIe-based connectivity SoCs

- Hands-on experience with hierarchical implementation and full-chip integration of large designs (>500M gates)

- Familiarity with EMIR, thermal, and package co-design considerations

- Experience mentoring senior engineers and driving methodology adoption across teams

Salary range is $185,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.