Astera Labs

Tech Lead Design Engineer

$133K–$185KFull-time · San Jose, CA
✓ Verified live on the employer's own system · added 6 days ago
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Mid-level · 5+ yrs exp

Requirements

Education: Bachelor's degree or related field

Experience: 5+ years

Skills & tools

HiringIc DesignTeam LeadershipTroubleshootingElectricalProgrammingEmbedded

Benefits — mentioned in this posting

Bonus / commission
Apply on company site ↗ See your fit → free

Full job description

Key Responsibilities

- RTL Design & Implementation

- Own RTL design for assigned blocks from microarchitecture through synthesis sign-off

- Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA

- Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality

- Cross-Functional Execution

- Partner with architecture to translate specifications into implementation-ready microarchitecture

- Collaborate with verification on testplans, coverage closure, and bug triage

- Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure

- Technical Leadership & Quality

- Mentor junior engineers and contribute to design methodology, scripts, and best practices

- Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments

- Drive structured, data-driven design decisions in support of aggressive tapeout schedules

Basic Qualifications

- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

- 5+ years of digital design experience, including at least one full chip from spec to tapeout

- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows

- Hands-on experience with timing closure, CDC, lint, and low-power design techniques

- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration

Preferred Qualifications

- MS or PhD in Electrical Engineering or Computer Engineering

- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs

- Familiarity with formal verification, emulation, or assertion-based methodologies

- Background in advanced process nodes (7nm, 5nm, or below)

- Strong debug skills across pre-silicon and post-silicon environments

Salary range is $133,200 to $185,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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This posting was published by Astera Labs on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.