Astera Labs

Principal Digital RTL Engineer

$185K–$240KFull-time · San Jose, CA
✓ Verified live on the employer's own system · added 6 days ago
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Senior · 8+ yrs exp

Requirements

Education: Doctorate or related field

Experience: 8+ years

Skills & tools

Ic DesignPcb DesignTeam LeadershipTroubleshootingProcess ImprovementElectricalCircuit DesignScripting

Benefits — mentioned in this posting

Bonus / commission
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Full job description

Key Responsibilities

- Circuit Design & Architecture

- Architect, design, and optimize high-speed analog/mixed-signal circuits such as SerDes, PLLs/clocking, ADCs/DACs, LDOs, and bias/reference blocks

- Define block-level specifications and trade-offs for performance, power, area, and yield in advanced process nodes

- Drive design methodology, reuse, and best practices across the AMS team

- Verification & Validation

- Develop and execute simulation plans across PVT, Monte Carlo, and reliability corners to ensure first-pass silicon success

- Partner with layout designers to guide floorplanning, matching, parasitics, and physical implementation

- Lead silicon bring-up, characterization, and debug, correlating measured results to models and specifications

- Technical Leadership & Collaboration

- Provide technical direction and mentorship to design engineers, elevating the capabilities of the broader team

- Collaborate cross-functionally with digital, system, product, and packaging teams to deliver integrated solutions

- Contribute to IP roadmaps, design reviews, and continuous improvement of the AMS design flow

Basic Qualifications

- MS or PhD in Electrical Engineering or a related field

- 8+ years of experience in analog/mixed-signal integrated circuit design

- Proven track record designing high-speed AMS blocks (e.g., SerDes, PLLs, data converters, references/regulators) through production silicon

- Strong command of transistor-level design, device physics, and analog design fundamentals in advanced CMOS nodes

- Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and scripting for design automation

- Demonstrated ability to take designs from specification through tape-out and silicon validation

Preferred Qualifications

- Experience with high-speed I/O and SerDes for connectivity standards such as PCIe, Ethernet, or UALink

- Deep understanding of physical-layer signal integrity, channel modeling, and equalization

- Hands-on lab experience with high-speed measurement and characterization equipment

- Familiarity with mixed-signal verification methodologies and analog/digital co-design

- Excellent communication skills and a collaborative, mentorship-driven approach in a fast-paced environment

Salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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This posting was published by Astera Labs on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.