Principal Hardware Systems Architect - Phased Array User Terminal

We are seeking a Principal Hardware Systems Architect to define and lead the end-to-end architecture of our next-generation satellite user terminal. In this role, you will own system-level hardware design across RF antenna arrays, high-speed digital processing, power systems, and mechanical integration.

You will drive the technical roadmap, make critical architectural and component trade-offs, and guide a cross-functional engineering team to deliver a high-performance, cost-optimized product at scale.

- Own the end-to-end system block diagram, defining the hardware architecture, power distribution, data pathways, and grounding schemes for the user terminal. - Evaluate and select critical components, including main SoCs, high-speed transceivers, memory, and peripherals, balancing performance, power efficiency, and bill-of-materials (BOM) cost. - Act as the primary technical anchor connecting RF, Electrical, Mechanical, and Embedded Software teams to resolve multi-disciplinary interface challenges. - Define the thermal dissipation strategy and high-voltage power delivery frameworks to support high-power beamforming states. - Drive the hardware through the entire product lifecycle from initial architecture to global, high-volume mass manufacturing, partnering closely with contract manufacturers (CMs) and suppliers to optimize assembly yields, execute factory test strategies, and reduce unit costs. - Establish the technical metrics, validation plans, and compliance strategies required for international wireless deployment (FCC Part 25/15, CE, ETSI).

- Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a highly related technical field. - 10+ years of hardware engineering experience, with 4+ years acting as a Principal Systems Architect or Lead Architect delivering complex wireless, radar, or satellite communication products. - Deep technical understanding of phased array antenna physics, digital beamforming architectures, high-speed digital buses (PCIe, SerDes, Ethernet), and RF front-ends. - Strong background in defining layout constraints for massive, multi-layer mixed-signal boards, with a focus on strict signal/power integrity and EMI containment. - Proven track record of architecting hardware intended for high-volume manufacturing, with deep knowledge of DFM/DFA constraints and supply chain trade-offs.

- Understanding of the interaction between RF-transparent radome polymers (like ASA or polycarbonates), hydrophobic coatings, and high-frequency microwave arrays. - Previous engineering leadership role in a major Low Earth Orbit (LEO) or Geostationary (GEO) user terminal development program.

Base Pay Range for: CA applicants is $230,773.00 - $323,081.85 WA applicants is $230,773.00 - $323,081.85