Senior/Staff Physical Design Engineer

As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations.

This role is fully on-site and in-person.

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE / Computer is required, and a Master’s degree is preferred.

• ≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.

• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.

• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.

• Block level ownership from architecture to GDSII, driving multiple complex designs to production.

• Experience with Cadence and/or Synopsys physical design tools/flows.

• Familiarity and working knowledge of System Verilog/Verilog.

• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.

• Experience in working with IP vendors for both RTL and hard-macro blocks.

Your base salary will be determined based on your experience and the pay of employees in similar positions. The base salary range is $135,000 USD - $165,000 USD for Senior Level, and $160,000 USD - $195,000 USD for Staff Level.