Tech Lead Physical Design Engineer, Power Integrity

Key

Responsibilities - Power Integrity Analysis & Sign-off - Own static and dynamic IR drop and electromigration analysis at block and full-chip levels, driving closure to foundry sign-off criteria - Drive UPF-based power domain planning and power-aware sign-off across multi-voltage designs - Analyze thermal and current density issues and recommend design modifications to ensure long-term reliability - Design Convergence & Cross-Functional Partnership - Collaborate with package, power grid, and floorplan teams to identify and resolve voltage drop hotspots and EM violations early in the design cycle - Provide actionable feedback to implementation teams on power grid reinforcement, decap strategy, and hard-macro / SerDes integration - Partner with RTL, STA, verification, IP vendors, and foundry to drive power integrity convergence through tapeout - Methodology & Automation - Develop and refine EMIR runsets, stimulus methodologies, and reporting dashboards to improve predictability and reduce iterations - Build and maintain EMIR analysis flows and automation infrastructure for efficient multi-corner analysis - Deliver clear, actionable root-cause analysis and mitigation guidance at both block and full-chip levels

Basic

Qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field - 5+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced nodes (7nm and below) - Deep expertise in power grid design, PDN analysis, and EM reliability mitigation, including static and dynamic IR methodologies and foundry sign-off criteria - Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC / PrimeTime PX - Strong scripting ability in Tcl, Python, and/or Perl for flow automation and data analysis

Preferred

Qualifications: - Master's degree in Electrical Engineering or a related field - Power integrity experience on high-speed SerDes, Ethernet PHY, or PCIe designs - Package-level power delivery analysis / co-simulation, including advanced packaging or multi-die integration exposure - Experience building EMIR methodology infrastructure that scales across multiple concurrent tapeout programs Salary range is $160,000 to $200,000 depending on experience, level, and business need.

This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.