ASIC Core DFT Technical Leader

The application window is expected to close on: 09/29/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

As an ASIC DFT Technical Leader, you will drive the definition, architecture, and implementation of cutting-edge Design-for-Test strategies across Cisco’s groundbreaking Silicon One portfolio. You will lead cross-functional integration from early-stage design through post-silicon validation, establishing scalable test logic, reusable code, and robust verification methodologies.

Bridging physical design, DV, and system validation teams, you’ll oversee complex functional areas and shape end-to-end electrical specifications for industry-defining hardware. In this high-visibility leadership role, your innovations will directly enhance design quality, yield, and time-to-market for some of the most advanced networking silicon on the planet.

• Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience

• Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and post silicon debug.

• Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime

• Prior verification experience including, System Verilog Logic Equivalency checking and validating the Test-timing of the design

• Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification

• DFT CAD development – Test Architecture, Methodology and Infrastructure

The starting salary range posted for this position is $214,100.00 to $309,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.