Senior DFT Engineer - LPU

- Define and implement SCAN, MBIST, and JTAG debug structures, applying sophisticated DFT techniques to drive post-Si testing plans.

- Build DFT timing constraints and partner with the Physical Design and STA sign-off team to ensure timing closure in DFT mode.

- Work closely with the post-silicon team to bring up test patterns on silicon, ensuring flawless bringup.

- Collaborate with the CAD methodology team to introduce innovative and intelligent AI driven optimizations, improving efficiency in DFT implementation.

- Bachelor's or M.S. in Computer Engineering or Electrical Engineering (or equivalent experience) with 5+ years of industry experience in DFT for high-performance ASICs.

- Practical experience with SCAN/MBIST/Test generation tools and processes for large SoC/ASIC.

- Domain expertise in DFT techniques such as ATPG, test pattern translation, yield learning, scan compression, MBIST, IEEE 1500 standard, and LBIST.

- Familiarity with ATPG Streaming SCAN Network (SSN) implementation.

- Experience with UDFMs like Cell Aware and Small Delay Defect.

- Consistent track record in yield estimation and test optimization.

- Experience working with real silicon in the lab and debugging DFT test sequences on ATE to resolve silicon issues.

- Solid understanding of RTL to GDS methodologies and formal equivalence.

- Outstanding interpersonal and organizational skills with a strong desire to work as part of a team with varied strengths.

Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

Applications for this job will be accepted at least until July 5, 2026.