Principal ASIC Test Development Engineer

Individual contributor role responsible for testability solutions of ASICs, memory, and 2.5D SiPs for Juniper's product development and manufacturing. Includes both structured ATE-level test as well as system-level/mission-mode (functional) environments.

- Responsible for developing test strategy and DFT (Design-for-Test) solutions for ASICs and 2.5D SiP (System-in-Package) that supports high test coverage requirements of components and systems.

- This role concentrates on Pre-P0 development and works between HW Eng development teams and Supplier Development Teams

- Works closely with design teams to enable the DFT features in ASICs, validate on ATE, integrate in diagnostics, and implement in manufacturing tests

- Development of innovative DFT IP in collaboration with cross-functional teams inside and outside the company

- Work closely with component engineers to resolve high DPPM ASIC issues at EMS partner sites

- Engage in test standard working groups, such as IEEE 1149, 1687, P1838, JC-42 Solid State Memories

- Trusted advisor on ASIC testability to Juniper teams including ASIC frontend, physical design, DFT, system software, diagnostics, hardware and manufacturing test teams. The influence occurs from the beginning (ASIC kick-off) to production release.

- Key advocate recognizing and solving structural vs functional test coverage gaps, as well as weaving in new fault models for advanced semiconductor technology nodes

- Demonstrated innovation via patents, published technical papers and conference presentations

- Ownership of ASIC test requirements for ASIC MRDs, phase exit validation, advanced test mode development, fault coverage attainment, achievement of manufacturability objectives and continuous improvement

- Voice of test authority with ASIC suppliers -- working closely with their product/test teams, quality, design engineering and technologists to correlate and eradicate ASIC failures in our systems with their wafer test, package test and BLCT-1. Able to independently solve NTF (No-Trouble-Found) supplier issues, via creating unique ATE-level tests to solve such issues, per strong knowledge of a chip's design.

- Responsible for influencing supplier testing to implement Juniper-favorable manufacturability modes at their production test

- Demonstrated Principal or Distinguished Engineer expertise

- A minimum of 15+ years of experience in testability and DFT area for ASICs, memories, and 2.5D SiPs

- Excellent knowledge of state-of-the-art DFT techniques in MBIST, IOBIST, LBIST, JTAG, scan/ATPG, and 1687

- Strong working level experiences on ASIC DFT implementation, post-silicon validation, debug, and diagnostic integration

- Exposure to various semiconductor test challenges and solutions for high-performance ASICs, TSV, HBM (High Bandwidth Memory) DRAM, 2.5D, and 3D ICs

- Broad experiences with ASIC suppliers, IP/EDA vendors, 2.5D SiP ecosystems partners, and contract manufacturers

- Excellent communication, collaboration and program management skill set. Able to independently influence others.

"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. - United States of America: Annual Salary USD 153,500 - 291,500 in Massachusetts // 153,500 - 310,500 in California // 135,000 - 310,500 in Texas The listed salary range reflects base salary.

Variable incentives may also be offered."