Senior Staff Engineer Digital IC Build Flow and Methodology

We are seeking a Senior Engineer to architect, implement, and maintain scalable build scripts and front-end methodology for complex digital IC designs. This role focuses on improving compilation, elaboration, simulation, and regression flow across block, subsystem, and full-chip designs, with an emphasis on performance, correctness, and developer productivity.

The ideal candidate combines strong software engineering skills with deep understanding of ASIC/SoC design workflows and EDA tooling and enjoys owning end-to-end infrastructure used daily by large design and verification teams.

Design, implement, and maintain chip design build flows supporting block, subsystem, full-chip, and multi-chip simulations.

Develop and own build scripts and orchestration logic for compile, elaborate, simulate, and regression workflows.

Improve build performance through dependency analysis, incremental builds, caching, and flow optimization.

Define and evolve methodology standards for front-end design and verification flows.

Architect and enhance CI / pre-submit verification flows to improve quality and turnaround time.

Integrate and support industry EDA tools within robust scripted flows.

Collaborate with RTL, DV, methodology, and infrastructure teams.

Bachelor's or Master's degrees in electrical engineering, Computer Engineering, Computer Science, or related field.

8+ years of experience in ASIC/SoC design, verification, or methodology roles.

Strong programming skills in Python and at least one of TCL, C/C++, or shell scripting.

Experience with next-generation or programmable build flows.