Principal Analog Circuit Design Engineer - SerDes

We are seeking a highly experienced and motivated Principal Analog Design Engineer to lead the design and validation of cutting-edge analog circuits for high-speed (112G and 224G) SerDes applications. In this role, you will be a key technical driver in the definition, execution, and validation of complex analog and mixed-signal designs.

This role involves providing technical direction and mentorship to layout and less experienced analog design engineers, fostering a collaborative and knowledge-sharing culture. You will engage closely with cross-functional teams, including systems, digital design, and test engineering, to ensure robust design implementation and validation.Strong problem-solving skills, analytical thinking, and a commitment to execution excellence are essential.

As a principal-level engineer, you will be expected to demonstrate a proven track record of delivering high-quality results in advanced FinFET CMOS technology within high-speed SerDes design environments. Excellent documentation and presentation skills are also required to clearly communicate complex design concepts and results.

The ideal candidate is self-driven, detail-oriented, and thrives in a fast-paced environment. You will actively participate in technical discussions across multiple disciplines, including analog/mixed-signal design, post-silicon validation, and system-level collaboration.

- Excellent communication, documentation, and presentation skills.

- Strong problem-solving attitude and ability to deliver under tight schedules in a collaborative environment.

- Demonstrated leadership in cross-functional technical discussions and decision-making.

- Team player with a collaborative mindset, willingness to share knowledge, and a hands-on approach to problem-solving

Master's degree in Electrical Engineering, Electronics Engineering, or related field.

- 8+ years of experience in analog/mixed-signal circuit design for high-speed SerDes applications.- Proven expertise in one or more of the following areas: PLL, CDR, CTLE, DFE, ADC, or Transmitter (TX) design.

- Strong understanding of high-speed communication standards such as PCIe (Gen5/Gen6) and Ethernet (100G/400G/800G).

- Solid foundational knowledge of analog design principles-noise, jitter, matching, stability, and linearity.

- Hands-on experience with advanced FinFET CMOS process technologies (7nm or below).

- Proficiency in analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent.

- Experience in silicon bring-up, post-silicon validation, and lab debug of analog circuits.

Ph.D. in Electrical Engineering, Electronics Engineering, or related field.

- 10+ years of experience in analog design for high-speed SerDes (56G/112G/224G) applications.

- Deep expertise in transmitter and receiver architecture, CDR loops, equalization techniques, and advanced ADC architectures.

- Familiarity with next-generation standards such as PCIe 6.0+, 800G/1.6T Ethernet, JESD, and other SerDes protocols.

- Hands-on experience in behavioral modeling (Verilog-A), MATLAB-based analysis, and automation scripting (Python/Tcl/Perl).

- Strong understanding of signal integrity, channel modeling, and system-level link performance.

- Proven ability to mentor junior engineers, guide layout implementation, and drive design reviews..

Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies).

The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Position of Trust This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position.

For additional questions, please contact your Recruiter.

Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.