Senior Principal Test Engineer

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

As the Senior Principal test engineer within the Operations, You’ll defines the IO Chiplet ATE test strategy, drives cross‑functional alignment, and leads development of ATE IP that enables robust qualification, comprehensive coverage, and efficient high‑volume manufacturing. As the primary technical authority, the role ensures test methodologies, infrastructure, and execution meet the performance, quality, and scalability requirements of the product roadmap.

• Lead the development of ATE test solutions for characterization, production, and wafer sort on the Advantest 93K platform, driving cutting‑edge test capability and ensuring products meet the highest quality standards.
• Design and develop high‑speed ATE hardware supporting data rates above 112 Gbps, advancing next‑generation test methodologies and enabling future‑ready semiconductor products.
• Create comprehensive test plans and methodologies aligned with stringent product specifications, ensuring robust validation and consistent product performance.
• Collaborate closely with DFx and Design teams to review testability and test strategies, contributing to improved yield, optimized test methodologies, and cross‑functional innovation.
• Convert design‑level test content into ATE‑ready test patterns, ensuring seamless transition from simulation to production environments.
• Drive test flow optimization, reducing test time, eliminating redundant steps, improving yields, and releasing high‑quality production test programs in partnership with cross‑functional engineering teams.

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related discipline
• Over 12 years of semiconductor test engineering experience, spanning new product introduction (NPI), ATE development, silicon characterization, correlation, and high‑volume manufacturing
• Proven technical leadership in high‑speed and high‑power semiconductor test development for AI, networking, and advanced compute products
• Deep expertise in ATE test methodologies, silicon process fundamentals, DFT/DFM, high‑speed SerDes, and high‑power ATE testing.
• Track record of building scalable ATE architectures and reusable ATE IP for MCM, CPC, and CPO product lines
• Strong skill on the Advantest 93K platform
• Proficient in Java, C/C++, Perl, Python, and Linux
• Strong communicator with excellent teamwork and problem‑solving capabilities
• Self‑driven, adaptable, and effective in fast‑moving, dynamic engineering environments

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.

Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.