ASIC DFT STA Engineer

The application window is expected to close on: 09/22/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

You will be in the Silicon One development organization as an ASIC DFT STA Engineer. You are a detail-oriented STA Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly.

As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

- Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience. - Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development. - Prior working experience in timing constraint development and verification. - Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.

- Masters degree + 10 years of relevant experience. - Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints. - Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST. - Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime. - Prior working experience with synthesis tools: Synopsys Fusion/design Compiler. - Prior working experience with Tessent tool like DFT insertion in RTL.

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.