STA Engineer

Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team.

The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-systems.

Qualcomm's Wi-Fi SoC organization is seeking an experienced and highly skilled Static Timing Analysis (STA) and Synthesis Engineer to contribute to the development of next-generation connectivity chipsets. This role focuses on driving timing-critical implementation for high-performance, low-power Wi-Fi solutions used across mobile, Access point (WIN), XR, automotive, and IoT platforms.

You will collaborate closely with Architecture, RTL design, Design verification, DFT, and physical design teams to deliver high-quality silicon on aggressive schedules. The responsibilities include the following

* Drive subsystem-level STA and timing closure for both pre-layout and post-layout phases, with support at full-chip level.

* Perform timing analysis using PrimeTime (or equivalent tools) and contribute to full-chip signoff activities.

* Identify timing bottlenecks, debug violations, and recommend micro-architectural or implementation-level optimizations.

* Develop and validate SDC constraints, including Multi-mode and multi-corner (MMMC) setup, to enable accurate and efficient STA analysis.

* Define and manage I/O timing budgets across hierarchical designs.

* Provide actionable timing feedback at block/HM, sub-system and full-chip levels, including root cause analysis and ECO guidance.

* Manage large-scale multi-corner/multi-mode STA runs with automation, partitioning, and efficient resource usage.

* Collaborate with RTL, synthesis, and physical design teams to ensure robust timing closure.

* Perform synthesis (including low power), formal verification (LEC), and low-power checks for complex SoCs, sub-systems, and cores.

* Validate synthesis QoR and ensure clean handoff to physical design.

* Balance Power, Performance, and Area (PPA) constraints during implementation.

* Develop AI-driven flows using TCL, Perl, and Python scripts to automate and enhance efficiency across STA, synthesis, timing-constraint development, ECO implementation, and low-power verification flows.

* 6-8 years of experience in ASIC/SoC STA, synthesis (including low power), timing constraint development, Low power checks and functional ECO implementation.

* Deep knowledge of Static Timing Analysis (STA), and timing constraints.

* Experience with Multi Mode Multi Corner (MMMC) timing closure, OCV/AOCV/POCV, and advanced technology nodes.

* Experience in Synthesis, Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist).

* Understanding of SOC clocking and reset methodology and implementation.

* Exposure to Low implementation techniques and design checks (multi-voltage designs, UPF).

* Implementation of Functional ECOs using Conformal ECO Tool.

* Familiarity with Low power design, Bus implementation (AXI/AHB) and Clock Domain Crossing (CDC)

* Familiarity with Wi-Fi, Bluetooth, or other wireless SoC design.

- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.

PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.