Senior Power Integrity Methodology CAD Engineer

- Developing physical design methodologies for rail analysis and signoff.

- Responsible for coming up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips.

- Crafting workflows and tool methodologies for power and noise analysis across multiple projects.

- Master's degree or equivalent experience in Electrical Engineering or related field.

- Minimum 5+ years of experience in EMIR flow methodology development and support.

- Strong understanding of all aspects of EMIR analysis and signoff.

- Familiar with hierarchical design approach and hierarchical signoff.

- Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.

- Ability to collaborate across teams: Strong interpersonal, communication and teamwork skills, with a track record of working closely with hardware and design teams to facilitate EMIR signoff

- Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.

- Adaptability and problem-solving skills: Ability to thrive in a dynamic, fast-paced environment where quick thinking and creative solutions are often required.

- Experience using AI tools to improve capabilities in the power integrity domain, such as automating analysis and improving tool/flow features

NVIDIA is widely considered to be one of the technology world's most desirable employers. And due to outstanding growth, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology?

If so, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

Applications for this job will be accepted at least until August 3, 2026.