Senior Staff Engineer, ASIC Design/Implementation -- LEC/STA/Power Analysis

We are seeking a highly skilled and experienced Timing/STA Engineer to join our team. The ideal candidate will have a strong background in timing constraints development, STA Signoff/Margins flows & methodologies for both SOC level and block level. They should have experience that includes running STA signoff flows, understanding of STA signoff margins, generating timing ecos, developing timing constraints, timing budgeting, optimization and timing closure of high-speed designs.

Additionally, experience with deep technology nodes such as 5nm/4nm would be valued.

- Develop and validate timing constraints for intricate SoC designs.

- Collaborate with Architecture, RTL, DFT, and Analog teams to understand the design requirements, analyze the timing complexities, and develop consolidated timing modes and constraints for sta signoff.

- Own and contribute to various sta related tasks like doing timing ecos for blocks and SoCs, developing custom scripts to create histograms, sta flow management, etc.

- Perform static timing analysis (STA) using industry-standard tools (e.g. Primetime).

- Define and implement timing signoff methodologies, including process corners, derates, and uncertainties.

- Resolve or find workarounds for tool issues, independently or working with EDA tool vendors.

- Conduct post-route timing checks and quality of results (QoR) analysis.

- Automate STA related processes/flow using scripting languages such as Tcl or Python.

- Create QoR dashboards, histograms for STA runs across all modes.

- Ensure compliance with timing signoff checklists and criteria.

- Document best practices and lessons learned to drive continuous improvements in future projects.

- Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.

- Minimum of 5 years of industry experience in ASIC timing and sta.

- Strong understanding of ASIC design flows, from RTL to GDSII.

- Knowledge and hands-on experience with sta methodologies and implementation.

- Proficiency in using STA tools, and scripting languages (e.g., Tcl, Perl).

- Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.

- Strong understanding of timing constraint development for hierarchical designs, timing ECO creation and final timing signoff.

- Familiarity with physical design and timing optimization techniques and strategies to achieve deterministic timing closure.

- Proven track record of delivering successful designs on time and meeting performance, power and area goals.

- Excellent problem-solving skills, attention to detail, and ability to analyze and debug complex issues.

- Strong communication and collaboration skills to work effectively within cross-functional teams.