IP Release Principal Engineer

- Own the full RTL static analysis sign-off flow including Lint, CDC (Clock Domain Crossing), and RDC (Reset Domain Crossing) checks using Industry standard tools.

- Review and approve RTL static waivers; ensure all waivers are justified, documented, and included in the IP release package.

- Drive front-end synthesis readiness for each IP subsystem using multiple EDA tools; validate synthesis scripts, timing constraints (SDC), and UPF.

- Work with IPSS COE Implementation Engineers to alidate that IP releases meet synthesis quality bars: clean Analyze/Elaborate, no unconstrained endpoints, and representative PPA metrics (area, timing, power).

- Ensure early DFT consideration is built into each IP subsystem - including scan insertion readiness, BIST hooks, JTAG, and boundary scan.

- Review RTL DFT handoff collateral (filelists, SDC, CDC constraints for DFT), and validate that IP packages are DFT-ready for downstream insertion flows.

- Serve as COE liaison to DFT teams; triage DFT-related blockers for IP releases and drive resolution across design and DFT engineering teams.

- Own and execute the IP delivery checklist at each milestone (iRTL, Code Complete, RTLF), verifying completeness of all required collateral including: RTL source files, file manifests (.f/.vc), SDC, UPF, memory lists, CDC crossing lists, static waivers, CSR/register descriptions, synthesis scripts, and integration guidelines.

- Ensure alignment of IP releases with requirements and delivery standards.

- Validate IP release packaging through IPMP and ensure versioned, traceable releases are distributed to SoC teams and external customers.

- Maintain and publish IP release quality dashboards and metrics (delivery status, checklist completion, open issues).

- Act as the primary technical point of contact for SoC integration teams consuming COE IP subsystems - triaging and resolving IP integration issues related to static checks, synthesis, and DFT.

- Manage IP delivery escalations; track bugs and action items in Jira; provide timely updates to consuming program teams.

- Provide integration guidance (RTL guidelines, constraints usage, CDC/RDC methodology, synthesis configuration) to SoC engineers adopting COE IP subsystems.

- Interface with third-party IP vendors to review quality metrics (Lint/CDC/RDC results, synthesis reports, DFT support) as part of IP onboarding and evaluation.

- Collaborate closely with TFM team, Central Engineering, SoC teams, DFT, PD, FW/SW, and emulation teams to ensure IP packages meet all downstream requirements.

- Participate in methodology working groups to align on Lint/CDC/RDC rule sets, tool selection, and checkpoint requirements.

- Contribute to AI automation to reduce manual effort and increase consistency of IP release flows.

- Bachelor's degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience or e quivalent professional experience in lieu of a formal degree

- Domain Expertise of SoC architecture, processor cores, memory, PCIE/CXL highly preferred

- Ethernet, Security and peripheral interfaces through hands on prior experience preferred

- Experience with Large and complex design synthesis, Floor planning, Place and Route, Clock tree and Timing closure of large Subsystems

- Extensive experience in Verilog and Static Quality checks of the implemented RTL

- Experience with leading foundries and latest process nodes 2nm, 3nm, 5nm etc preferred

- Hands on experience in interpretive language such as Perl/Python

- Proven track record of delivering production-quality designs on aggressive development schedules

- Good communication skills and self-discipline contributing in a team environment