Design Verification Senior Staff Engineer

- Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field

- Strong knowledge of PCIE and CXL protocols and architecture

- Familiarity with industry-standard tools (e.g., simulation, waveform debugging, coverage tools)

- Exposure to emulation platforms (e.g., Palladium, Veloce) a plus

- Develop and execute verification plans for high-speed memory interfaces (PCIE 6/7, CXL 3.2/4.0)

- Build and enhance UVM/System Verilog-based verification environments

- Develop test benches, sequences, and checkers for functional and performance validation

- Perform protocol-level verification for PCIE controllers and PHY interfaces

- Analyze and debug simulation failures, identify root causes, and drive resolution

- Work closely with design, architecture, and firmware teams to ensure coverage closure and spec compliance

- Contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage

- Support emulation/FPGA validation and post-silicon bring-up (nice to have)

- Review design specifications and provide feedback for testability and robustness