Senior Testchip SoC Physical Design Engineer (Integration & Methodology)

Join the Design Technology Platform (DTP) organization within Intel Foundry as part of the X-Chip SoC Full-Chip Integration team. This team plays a critical role in enabling next-generation semiconductor innovation by delivering testchip platforms that validate advanced process technologies and support high-volume manufacturing readiness.

In this role, you will contribute to the development of physical design methodologies and drive full-chip SoC integration for cutting-edge testchip vehicles. You will collaborate across design, process, and manufacturing teams to ensure high-quality, scalable solutions for advanced technology nodes.

- Developing layout design methodology for testchip development in next generation process nodes - Working closely with Process Integration, Yield and QnR to define critical Design features that need to be exercised in the early lead vehicle test chips. - Establishing, orchestrating, overseeing, and maintaining hierarchical layout design specifications for correct-by-construction integration - Building and executing tactical plans to converge hierarchical SOC layout design against aggressive schedule requirements by working closely with PDK teams - Driving all aspects of physical design convergence, including preparing layout hierarchy for design tape-in, debugging and resolving issues uncovered by verification tools - Working with tool/flow owners and vendors for ongoing tool/methodology improvement

- Exhibiting strong interest in Layout design in advanced technology nodes. - Strong verbal and written communication skills - Ability to work well both autonomously and in an intensive, cooperative team environment - Coordinate between different stakeholders for testchip to arrive at execution commit for testchip - Motivation to continuously learn and drive to push improved layout productivity and efficiency

- Work on cutting-edge semiconductor technologies that shape the future of computing - Collaborate with industry-leading experts across design and manufacturing - Opportunities for career growth and technical leadership - Contribute to innovations that impact global technology at scale - Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life

Minimum qualifications are required to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

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Master's degree in electrical engineering or related field with minimum of 5 years of experience in the following areas:

- Experience with physical/layout design in advance technology nodes - In Layout design tools like Cadence Virtuoso Suite or Synopsys Custom Compiler - Design rules and layout constraints in advanced semiconductor processes - Experience with floorplanning, hierarchical design integration, and layout verification/debug

- Experience in Definition of Testchip/Product design from Concept to Execution Commit

- Experience in working with Foundry teams on negotiating features to exercise in design - Proven Project Management skills on coordinating and tracking the entire design cycle of a project from Feature definition to final Tape-in - Previous related work experience in a semiconductor foundry preferred

Additional Locations: US, California, Santa Clara, US, Texas, Austin

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.