Senior Custom ASIC Engineering Lead

Are you a versatile, senior engineer capable of leading external and internal cross-functional teams in areas such as physical design, STA, DFT, and packaging? Have you taped out so many chips that you can identify potential design problems hidden in EDA reports, advise design teams on how to fix them, and then publish an application note about avoiding them in future?

Do you love technical-deep-dive with engineers and providing an eagle's eye summary to management? If this is your engineering profile and you are looking for a challenge, then we have one for you.

Broadcom develops critical Infrastructure chips that enable a variety of Customers to produce ASICs in almost all major segments of the Semiconductor industry, including AI. Our ASIC Products Division is looking for a senior engineer to guide customer teams designing challenging chips in areas such as AI, HPC, networking and storage.

This is an immensely responsible position, and an opportunity to push the frontiers of technology by working with cross-functional teams inside and outside of Broadcom.

As a valued member of this team, you will be required to do the following:

- Manage external customer ASIC programs from inception to finish, including RFQs, technology and IP collaterals, design, test, packaging, fabrication, bring-up and production

- Advise customers on best practices in EDA, flows and design methodologies, and by organizing Q&A sessions with Broadcom technology experts

- See ahead, plan ahead, work ahead. Proactively assess potential risks to the design quality and project schedule, then work with cross-functional teams to prepare and execute risk mitigation actions

- Execute physical design flows to check that incoming customer tape-in netlists meet Broadcom's stringent tape-out quality standards

- Motivate and drive yourself to stay abreast of developments in Broadcom IPs, technology and end user applications

- Participate in discussions about your chips with marketing, sales, legal and regulatory compliance teams

- Be a consummate team player and assist other teams in need

You must have these proven skills to qualify for this position:

- Analyze PPA tradeoffs involved amongst various library components, and architectures

- Hands-on experience in physical design and STA, EDA tools, design flows for physical design, logic simulation, test, and packaging

- Logic design, chip architecture, microarchitecture, Verilog RTL coding Front-end logic design verification, DRC, logic synthesis

- Knowledge of DFT methods including scan, memory BIST and repair

- Bachelors degree and 12+ years of related experience; or Masters degree and 10+ years of related experience

The annual base salary range for this position is $143,800 - $230,000.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.