Design Verification Engineer (Silicon Engineering)

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe.

These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

- Responsible for digital ASIC verification at block and system level

- Write and review test plans, develop test harnesses and test sequences

- Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks

- Responsible for test plan execution, running regressions, code and functional coverage closure

- Automate test case generation by using Python and MATLAB programs

- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation

- Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

- Bachelor's degree in electrical engineering, computer science or computer engineering

- 1+ years of experience with design verification and test bench development

- Advanced degree in electrical engineering or computer engineering

- Expertise in developing test plans, implementing coverage models, and analyzing results

- Experience with scripting languages, e.g. Python for automation

- RTL design, chip bring-up, and post-silicon validation experience

- Ability to work in a dynamic environment with changing needs and requirements

- Ability to work extended hours and weekends as needed to meet critical milestones