SpaceX

Design Verification Engineer (Silicon Engineering)

$135KFull-time · Palo Alto, CA
✓ Verified live on the employer's own system · added 27 days ago
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Junior · 1+ yr exp

Requirements

Education: Bachelor's degree

Experience: 1+ year

What this role involves

UVMSystemverilogRTLAsicFunctional CoverageVerilogConstrained Random

Skills & tools

Ic DesignPythonMatlabElectricalScriptingEmbedded

Benefits — mentioned in this posting

Equity / stockBonus / commission401(k) / retirementHealth, dental & visionFamily / parental leavePaid time off
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Full job description

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe.

These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

- Responsible for digital ASIC verification at block and system level

- Write and review test plans, develop test harnesses and test sequences

- Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks

- Responsible for test plan execution, running regressions, code and functional coverage closure

- Automate test case generation by using Python and MATLAB programs

- Contribute towards pre-silicon verification, chip bring-up and post-silicon validation

- Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

- Bachelor's degree in electrical engineering, computer science or computer engineering

- 1+ years of experience with design verification and test bench development

- Advanced degree in electrical engineering or computer engineering

- Expertise in developing test plans, implementing coverage models, and analyzing results

- Experience with scripting languages, e.g. Python for automation

- RTL design, chip bring-up, and post-silicon validation experience

- Ability to work in a dynamic environment with changing needs and requirements

- Ability to work extended hours and weekends as needed to meet critical milestones

Pay range: Design Verification Engineer/Level I: $135,000.00 - $155,000.00/per year Design Verification Engineer/Level II: $155,000.00 - $210,000.00/per year

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan.

You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year.

Exempt employees are eligible for 5 days of sick leave per year.

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This posting was published by SpaceX on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.