Distinguished Engineer - Memory Subsystem Center of Excellence (CoE), Custom Silicon

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

The Distinguished Engineer, Memory Subsystem CoE is the senior-most technical authority responsible for end‑to‑end technical ownership of memory subsystems across all programs, customers, and SoCs. This role serves as the single technical point of accountability from architecture through post‑silicon validation and customer engagement.

The Chief Engineer ensures delivery of platform‑ready, reusable memory subsystems spanning DDR4/DDR5, LPDDR5/5X, and HBM4/HBM4e, aligned to JEDEC standards and long‑term product roadmaps. The role partners closely with Architecture, SoC teams, PCIe/Ethernet/Security CoEs, PHY vendors, and customers to ensure quality, predictability, and scalability of memory subsystem delivery.

• Own the Memory Subsystem TFM and technical roadmap across current, next‑generation (N+1), and future (N+2) platforms.

• Act as the final technical authority for architecture, micro‑architecture, RTL, DV, PHY integration, and system validation decisions.

• Define and maintain reference architectures, configuration models, and integration guidelines for memory subsystems.

• Drive sign‑off criteria, quality gates, and KPIs across architecture, DV, and validation.

• Partner with Memory CoE leadership to ensure consistent execution across multiple programs and sites.

• Guide cross‑functional teams (architecture, RTL, DV, PHY, FW/SW, validation) to deliver reusable, platform‑quality subsystems—not point solutions.

• Review and resolve cross‑program technical issues and escalations.

• Serve as the first technical point of contact for customers on memory subsystem architecture, features, and roadmap.

• Engage with ecosystem partners (JEDEC, IP vendors, PHY providers) on standards adoption, interoperability, and enablement.

• Support customer engagements, design reviews, and post‑silicon debug when required.

• Align memory subsystem evolution with SoC, compute, AI, and interconnect roadmaps across the company.

• 10+ years of experience in memory subsystem, SoC, or IP development.

• Expertise in DDR4/DDR5, LPDDR5/5X, and/or HBM architectures and system integration.

• Background in architecture, RTL, verification, and silicon bring‑up.

• Proven track record owning complex subsystems end‑to‑end across multiple products.

• Experience working directly with customers and external partners.

• Strong technical leadership and decision‑making skills in multi‑site environments.

• Experience defining reusable subsystem platforms or Centers of Excellence.

• Familiarity with CHI/AXI‑based SoC fabrics and cross‑subsystem interactions.

• Prior role as Chief Engineer, Fellow, or equivalent technical authority.

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.

Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com .

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S.

Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C.

1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-VP1