Senior Staff ASIC CAD Flow Infrastructure Engineer

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

We are seeking a highly motivated and technically strong ASIC CAD Flow & Infrastructure Engineer to drive the development, deployment, and support of next-generation ASIC design infrastructure. This role is responsible for defining scalable EDA methodologies, automation frameworks, and design flows that enable efficient development of complex SoCs across multiple product generations.

The ideal candidate combines deep semiconductor design-flow knowledge with software engineering expertise. The individual will collaborate closely with Design, Physical Design and IT teams to deliver robust, high-performance CAD solutions that improve engineering productivity and design quality.

• Develop and maintain CAD frameworks using Python, Tcl, Shell, and modern software engineering practices

• Build flow orchestration systems, dashboards, analytics, and monitoring tools

• Developed and maintained automation frameworks for integrating standard-cell libraries, memory macros, and IP blocks across multiple ASIC design and implementation flow entry points

• Establish best practices for synthesis and physical implementation

• Develop standardized flow frameworks that maximize reusability, maintainability, and automation

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience or e quivalent professional experience in lieu of a formal degree

• At least 5+ years of experience in ASIC CAD, EDA, design methodology, or infrastructure engineering. 8+ years prferred.

• Strong understanding of ASIC/SoC development lifecycle from RTL through tapeout

• Experience supporting commercial EDA tools from Synopsys, Cadence, Siemens EDA, or equivalent

• Familiarity with data analytics, telemetry, and AI-assisted design methodologies

• Strong cross-functional leadership and communication skills

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition.

Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.