Hudson River Trading

Design Verification (DV) Engineer

Full-time · Austin, TX +4 more
✓ Verified live on the employer's own system · added 102 days ago
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Junior · 2+ yrs exp

Requirements

Education: Bachelor's degree or related field

Experience: 2+ years

Skills & tools

Ic DesignMachine LearningTroubleshootingDevopsElectrical
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Full job description

The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.

These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith.

You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.

FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment.

No financial experience is necessary.

  • Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
  • Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
  • Managing test suites and continuous integration infrastructure
  • Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
  • Experience with code and functional coverage collection/analysis
  • Experience with SystemVerilog and industry-standard frameworks such as UVM
  • A bachelor’s degree in computer science, electrical engineering, or a related field

The estimated base salary range for this position is 175,000 to 250,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience. This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package.

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This posting was published by Hudson River Trading on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.