Insilico Medicine

Design Verification Engineer

Contract · Irvine, CA

✓ Verified live on the employer's own system · added 3048 days ago

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What this role involves

AsicDesign Verification

Skills & tools

Ic Design

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Full job description

Job Title: Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension)

Job Description: Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC: 1. PCIE verification background 2. 400G MAC verification background

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This posting was published by Insilico Medicine on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.