CPU Server Physical Design Timing Engineer

the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability.

In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows.

One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU.

You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3.

* STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores.

* Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.

* Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.

* Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.

* Evaluate multiple timing methodologies/tools on different designs and technology nodes.

* Work on automation scripts within STA/PD tools for methodology development.

* Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment

* Strong experience in design automation using TCL/Perl/Python.

* Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

* Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling

* Have experience in driving timing convergence at Chip-level and Hard-Macro level

* In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling,

* Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)