Senior ASIC Design Verification Engineer

The application window is expected to close on: 10/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. As an ASIC Design Verification Engineer, you will play a critical role in developing Cisco’s revolutionary data center, AI networking solutions. Join us to power the future of the digital world.

• Architect, develop, and maintain block, cluster, and top-level Design Verification environment infrastructure; Perform end-to-end verification of design blocks and top-level

• Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, post silicon bring up and performance analysis.

• Ensure comprehensive verification coverage through code and functional coverage implementation and review

• Collaborate with designers, architects, software teams, and vendors

• Lead multiple tasks efficiently with clear written and verbal communication

• Cultivate partnership and promote collaboration among team members

• Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC related experience, or Master’s degree in Electrical or Computer engineering and 4+ years of ASIC related experience, or PhD in Electrical or Computer engineering + 1 year of ASIC related experience

• Experience with ASIC design and verification processes, debugging, methodology, and tools.

• Experience in verifying blocks/clusters/full chip level for ASIC.

The starting salary range posted for this position is $167,700.00 to $245,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.