Cisco

ASIC Design Verification Engineering Leader

$214KFull-time · San Jose, CA
✓ Verified live on the employer's own system · added 6 days ago
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Mid-level · 5+ yrs exp

Requirements

Education: Bachelor's degree

Experience: 5+ years

Skills & tools

SecurityIc DesignTroubleshootingEmbeddedTeam LeadershipCloud PlatformsScriptingPython
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Full job description

The application window is expected to close on: 10/20/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

Come join us and take part in shaping Cisco’s revolutionary solutions for data centers by designing some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a unique combination of a startup culture with the benefits of working for the leading networking company in the world!

As an ASIC Design Verification Leader, you will play a pivotal role in driving Cisco’s next generation of revolutionary data center solutions. By architecting and building cutting-edge DV infrastructure from scratch across block, cluster, and top-level environments, you will ensure maximum functional coverage and elite quality for highly complex silicon.

You will collaborate closely across design, emulation, and software teams—debugging critical firmware issues and taking charge during hands-on ASIC bring-up. Ultimately, your technical leadership will guarantee seamless integration and optimal performance for the hardware platforms powering tomorrow's cloud infrastructure.

  • Typically: Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience
  • Prior experience with Verilog, SystemVerilog, and UVM within the last 2-3 years.
  • Prior experience with scripting languages (i.e Perl or Python)
  • Prior experience with ASIC design and verification processes, debugging, methodology, and tools.
  • Prior experience in verifying blocks/clusters or full chip level for ASIC.
  • Strong domain experience on one or more protocols – PCIe, Ethernet, RDMA, TCP, Fiber Channel (FC)
  • Experience with Formal verification (iev/vc formal/Jasper Gold)
  • Experience with AI agents (i.e Cursor, Codex, CoPilot, etc…)

The starting salary range posted for this position is $214,100.00 to $309,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Non-Metro New York state & Washington state: $192,400.00 - $317,200.00

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This posting was published by Cisco on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.