Cisco

ASIC Engineering Technical Leader- STA

$214KFull-time · San Jose, CA
✓ Verified live on the employer's own system · added 6 days ago
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Junior · 2+ yrs exp

Requirements

Education: Bachelor's degree

Experience: 2+ years

Skills & tools

Ic DesignFinancial Analysis
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Full job description

The application window is expected to close on: 09/11/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As a member of the team, you will contribute to defining innovative ASIC STA methodologies and creating robust flows essential for developing our complex chips.

Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality.

Help define the process, methods, and tools for design and implementation of complex developments.

  • Bachelor’s with 10 years of related experience, or Master’s with 5 years of related experience, or PhD with 2 years of related experience.
  • Prior experience with Integration for STA including Hyperscale and hierarchical analysis with parasitic stitching, IO budgeting, and flat parasitic extraction.
  • Prior experience in developing timing constraints and signing off timing on blocks/sub system in advanced process nodes
  • Prior experience with timing closure with various timing ECO including transition, setup, hold, noise, xtalk, and power recovery.
  • Prior experience with various on-chip variation including AOCV, POCV and voltage, temperature, aging-based timing derates.
  • Parasitic Extraction : Synopsys, Star-RCXT, Cadence Quantus
  • Static Timing Analysis & ECO: Synopsys Primetime/PTPX/Tweaker/PrimeClosure, Cadence Tempus

The starting salary range posted for this position is $214,100.00 to $309,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Non-Metro New York state & Washington state: $192,400.00 - $317,200.00

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