ASIC DFT Technical Leader

The application window is expected to close on: 10/02/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio.

Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

You will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips.

You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10 years of experience.
• Prior experience in post-silicon debug experience from first silicon to production
• Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Prior experience working with Gate level simulation, debugging with VCS and other simulators.

• Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development - Test Architecture, Methodology and Infrastructure
• Test Static Timing Analysis
• Post silicon validation using DFT patterns.
• Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

The starting salary range posted for this position is $214,100.00 to $309,800.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.