ASIC Physical Design Technical Lead

The application window is expected to close on: 08/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

- Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints

- Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan

- Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Handson experience with Fullchip clock mesh and Flex-HTree methods

- RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.

- Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.

- Work closely with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable best-in-class design methodology.

- Work with Foundry and standard cell IP vendors to define the signoff methodologies and validate/adjust them when you receive feedback from Post-Silicon Validation teams

- Bachelor's Degree in Electrical Engineering with 8+ years of Physical Design experience or Master's Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience.

- Experience with RTL2GDSII flow and design tapeouts in 7nnm/5nm/3nm or below process technologies.

- Experience working with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre/Pegasus.

- Experience working on Fullchip activities; including floor-planning, power-grid planning, partitioning and pin-assignment.

- Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis.

- Experience with static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.

- Experience with custom clock (H-Tree or Mesh) at chip level.

- Experience with Python and usage of AI tools by giving accurate prompts

The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.