Cisco

ASIC Design Engineer Technical Lead

$187KFull-time · San Jose, CA
✓ Verified live on the employer's own system · added 12 days ago
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Mid-level · 3+ yrs exp

Requirements

Education: Bachelor's degree

Experience: 3+ years

Skills & tools

Ic DesignTeam LeadershipTroubleshootingRoot Cause AnalysisElectricalScriptingPython
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Full job description

The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

- Participate in and contribute to chip architecture definition and discussions.

- Author design specifications and participate in micro-architecture specification reviews.

- Implement Verilog RTL to meet timing and performance requirements.

- Mentor junior engineers on performing project tasks and problem solving.

- Collaborate with the verification team to address design bugs and close code coverage.

- Work closely with physical design team to close design timing and place-and-route issues.

- Triage, debug, and root cause simulation, software bring-up, and customer failures.

- Perform diagnostic and post silicon validation tests in the lab.

- Bachelor's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience, or Master's degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical Engineering or Computer Engineering + 3 years in ASIC Design experience.

- Experience delivering ASIC designs from specification to tape-out.

- Experience in architecture and micro architecture development.

- Experience resolving setup and hold timing violations with RTL modification.

- Scripting experience (Python, Perl, TCL, shell programming).

The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Non-Metro New York state & Washington state: $166,300.00 - $274,100.00

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This posting was published by Cisco on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.