Cisco

ASIC DFT Technical Leader- MBIST

$211KFull-time · San Jose, CA
✓ Verified live on the employer's own system · added 26 days ago
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Senior · 10+ yrs exp

Requirements

Education: Bachelor's degree

Experience: 10+ years

Skills & tools

Ic DesignElectricalTeam LeadershipScriptingPythonCommunications
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Full job description

The application window is expected to close on: 09/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

You will be part of the Silicon One development organization as an ASIC Technical Lead- MBIST engineer. As a member of this team you will be involved in crafting cutting edge next generation networking chips.

- You will be leading the MBIST methodology in silicon one chips.

- Design & implement robust and reusable MBIST architecture.

- Spec comprehensive MBIST architecture and implementation agnostic to technology and tools.

- MBIST requirement definition for advanced technology nodes & advanced tech packages.

- Bachelors in Electrical engineering with at least 12+years (or Master's with 10+ years) of experience in ASIC DFT.

- Prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes.

- Prior experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent).

- Scripting skills (Python, TCL, Perl) for automation of test generation and analysis.

- Strategic Skills: Ability to plan and execute complex test strategies, excellent communication skills for cross-team collaboration, and a focus on silicon quality and yield improvement.

- Experience addressing Memory failure correlation in production.

The starting salary range posted for this position is $210,600.00 to $305,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Non-Metro New York state & Washington state: $189,300.00 - $312,200.00

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