ASIC Design Verification Engineering Technical Leader

The application window is expected to close on: 09/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received .

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms-like Silicon One-are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development-from design to qualification to production-is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

- Participate in the ASIC design verification for Cisco high-end switching products.

- Lead, architect, develop, and maintain block, cluster, and top-level Design Verification (DV) environment infrastructure.

- Develop simulation models, test plans, direct and random tests, code or functional coverage, multi-chip/system simulation, and performance analysis.

- Construct testbenches components like scoreboard, agents, sequencers, and monitors.

- Collaborate with designers, architects, and software teams to debug issues during post-silicon bring-up and integration and customer failures.

- Ensure comprehensive verification coverage through code and functional coverage implementation and review.

- Participate in and contribute to chip architecture definition and discussions.

- Mentor junior engineers on performing project tasks and problem solving.

- Bachelor's degree in Electrical or Computer engineering and 10+ years of ASIC Design and Verification experience or Master's degree in Electrical or Computer engineering and 8+ years of ASIC Design and Verification experience.

- Experience with ASIC design and verification processes (with System Verilog), debugging, methodology, and tools.

- Experience in leading the verification methodology (in UVM) of clusters/subsystems or full chip level for ASIC.

- Dashboard management for regression, coverage, test list completion and other DV statistics.

- Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS

The starting salary range posted for this position is $183,800.00 to $263,600.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.