ASIC DFT STA Technical Lead

- Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs. - Check timing for unconstrained endpoints, no clock, etc. - Your role may include SDC validation, CDC delay check, and SDC flow development. - Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience - Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development. - Prior working experience in timing constraint development and verification. - Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.

- Masters degree + 15+ years experience. - Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints. - Prior working experience with RTL design, CDC/RDC and conformal verification. - Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST. - Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime. - Prior working experience with synthesis tools: Synopsys Fusion/design Compiler. - Prior working experience with Tessent tool like DFT insertion in RTL.

The starting salary range posted for this position is $168,800.00 to $241,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.