SpaceX

ASIC/SOC DFT Engineer (Silicon Engineering)

$135KFull-time · Palo Alto, CA
✓ Verified live on the employer's own system · added 3 days ago
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Requirements

Education: Bachelor's degree

Skills & tools

Ic DesignTroubleshootingElectricalEmbedded

Benefits — mentioned in this posting

Bonus / commissionEquity / stock401(k) / retirementHealth, dental & visionFamily / parental leavePaid time off
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Full job description

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe.

These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

- Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools

- Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems

- Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage

- Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals

- Run and debug non-timing and SDF annotated gate level simulations

- Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation

- Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

- Bachelor's degree in electrical engineering, computer engineering or computer science

- Understanding of ASIC design flow, methodologies, physical design, and verification

- Experience with high reliability design and implementations

- Familiar with implementation or integration of design blocks using Verilog/SystemVerilog

- Familiar with UPF (unified power format), formal verification, and DRC rule checking experience

- Ability to work in a dynamic environment with changing needs and requirements

- Team-player, can-do attitude, and ability to work well in a group environment while still contributing on an individual basis

- Must be willing to work extended hours and weekends as needed

Pay Range: Level 1: $135,000.00 - $175,000.00 Level 2: $155,000.00 - $210,000.00

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short and long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks.

You may also accrue 3 weeks of paid vacation and will be eligible for 10 or more paid holidays per year. Employees accrue paid sick leave pursuant to Company policy which satisfies or exceeds the accrual, carryover, and use requirements of the law.

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This posting was published by SpaceX on their own careers system and is shown here with a direct link to apply there. Employers: for corrections or removal, contact jobs@veritahire.com.