R&D Engineer IC Design 5

This individual will be a key member of the ASIC system-level verification team.

Responsibilities include developing complex verification environments, creating comprehensive test plans, and verifying high-performance network switch ASIC/FPGAs. The role involves hands-on implementation across every aspect of ASIC verification while collaborating closely with system architects, design engineers, and verification teams.

The ideal candidate will have a proven track record of completing multiple successful ASIC design and verification cycles-from architecting testbenches (networking background preferred) to achieving full verification closure.

- Experience: 8+ years of ASIC design/verification experience, including a complete understanding of Verilog design and hands-on experience with C/C++.

- Methodologies & Languages: Strong working knowledge of object-oriented programming (OOP) and modern ASIC verification flows (e.g., UVM/SystemVerilog).

- Technical Depth: Complete mastery of Verilog for simulation and familiarity with ASIC design flows for deep sub-micron technologies.

- Domain Knowledge: Experience with networking protocols (e.g., Ethernet, PCIe, routing/switching) is a major plus.

- Track Record: Must have completed multiple ASIC tape-outs, with at least one project taken from initial concept through full production.

- Communication: Fully comfortable with technical and business English across documentation, cross-functional collaboration, and executive communications.

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.