Senior FPGA Design Verification Engineer

- Verification of FPGA's on daVinci systems for RTL functional correctness - Starting from test-planning to closing verification using coverage metrics - Hands-on testbench development UVM - Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model - Write constrained random stimulus and Implement functional cover groups - Debugging failures, bug tracking, and analyze and close coverage

- Advanced knowledge of HVL methodology (UVM) - Expertise in HVL and HDL (SystemVerilog, Verilog) - Experience defining coverage space and writing coverage models - Team player with excellent communication skills and the desire to take on diverse challenges - Experience writing scripts in languages such as Perl/Python - Solid verification skills in problem solving, constrained random testing, and debugging - Experience with Emulation/FPGA prototyping and Formal is a plus - Experience with ML-assisted flows, and agentic-AI automation frameworks to accelerate coverage closure, improve debug efficiency, and enhance overall verification throughput

We provide market-competitive compensation packages, inclusive of base pay, incentives, benefits, and equity. It would not be typical for someone to be hired at the top end of range for the role, as actual pay will be determined based on several factors, including experience, skills, and qualifications. The target compensation ranges are listed.

Required Education, Skills & Experience

• Advanced knowledge of HVL methodology (UVM)
• Expertise in HVL and HDL (SystemVerilog, Verilog)
• Experience defining coverage space and writing coverage models
• Team player with excellent communication skills and the desire to take on diverse challenges
• Experience writing scripts in languages such as Perl/Python
• Solid verification skills in problem solving, constrained random testing, and debugging
• Experience with Emulation/FPGA prototyping and Formal is a plus
• Experience with ML-assisted flows, and agentic-AI automation frameworks to accelerate coverage closure, improve debug efficiency, and enhance overall verification throughput Roles & Responsibilities

• Verification of FPGA’s on daVinci systems for RTL functional correctness
• Starting from test-planning to closing verification using coverage metrics
• Hands-on testbench development UVM
• Work closely with the design team to review specifications and architecture, extract features, define verification plan & coverage model
• Write constrained random stimulus and Implement functional cover groups
• Debugging failures, bug tracking, and analyze and close coverage