ASIC Design Verification Engineer (Santa Clara, CA)

Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products.

This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer

The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking).

Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency.

* Minimum 3 years of DV experience using uvm/assertion based verification technologies

* Experience with caches and DDR memory protocol verification

* Exposure with multiple succesfull tapeouts from conception to post silicon debug

- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.