ASIC Design Engineer

Qualcomm-Atheros, a.k.a. QCA http://www.qualcomm.com/qca/ is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team you will be working with WiFi (802.11x) technology, SOC infrastructure, chip level verification and employ best-in-class Design and verification methodology.

The candidate will be responsible for micro-architecture, RTL design, and development of new functional blocks, as well as subsystem and full-chip integration. This role is hands-on and requires ownership of the design through the complete ASIC lifecycle, from concept through tape-out. The candidate will collaborate closely with other subsystem teams to ensure smooth integration of releases, while interfacing with verification, DFT, FPGA emulation, and implementation teams.

* 5+ years of industry experience in ASIC design, micro-architecture, and design integration,

* Strong background in SoC micro-architecture, including specification, definition, and implementation of functional blocks.

* Hands-on experience with multi-domain clocking implementation in SOCs including understanding of clocking architectures, clock/power domain partitioning.

* Experience in Design linting and CDC analysis, including triage and closure of violations.

* Solid understanding of AMBA bus protocols, including AHB and APB.

* Exposure to AI/ML based design methodologies is a strong plus

- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

* Experience with ARM CoreSight architecture and debug interfaces.