CPU Server Floorplan and Integration Engineer

We are looking for highly talented, innovative, teamwork-oriented individuals for our cutting-edge technology work!

We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. By joining our team, you'll collaborate with world-class engineers to create innovative solutions that push the limits of performance, energy efficiency, and scalability. Our focus is on developing server-class high performance CPU solutions that are highly optimized for the needs of the server product.

As a CPU Floorplan and Integration Engineer, you will work with microarchitecture, RTL design and physical design teams to design, floorplan and integrate the CPU designs meeting aggressive power, area and performance goals using industry standard tools/flows.

* Proficiency in synthesis, place and route, and signoff timing/power analysis.

* Expertise in block-level implementation as well as full chip floorplanning and power grid planning.

* Skilled in physical design, integration, and verification of large processor and system-on-chip (SoC) designs.

* Extensive knowledge of low power and high-performance design methodologies.

* Strong understanding of circuit and layout design principles.

* Proven ability to work effectively within a team environment.

* In-depth understanding of extraction, static timing analysis (STA), and electromigration and IR drop (EMIR) flows and methodologies.

- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 1+ year of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.

* Experience in deep submicron process technology nodes is strongly preferred.

* Experience as a key technical lead driving development and delivery of physical design databases is a plus

* Solid understanding industry standard tools for synthesis, place & route and tapeout flows.

* * Ensure the designs are validated for functional and electrical robustness.

* Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP integration, power/ground generation, and pin assignment.

* Oversee full chip floorplan, area optimizations, block partitioning, and pin assignments.

* Manage chip-level place and route, and finalize the CPU database for construction and verification.

* Collaborate with external teams to fulfill IP technical and delivery requirements.